Assessment of Interface Trap Charges on Proposed TFET for Low Power High-Frequency Application

Accumulation of trap charges at the semiconductor and oxide interface is most dominating factor cannot be neglected as it degrades device performance reliability. This manuscript, presents detailed investigation to analyze impact (ITCs) on parameters proposed i.e., heterogeneous dielectric dual metal gate step channel TFET (HD DMG SC-TFET). The comparative study conducted with TEFT (DMG shows improved current carrying capability, suppressed ambipolar behaviour steeper subthreshold swing. purpose this determine ITCs DC characteristics analog/RF electrical device. It further observed that exhibit superior due engineering layer. Moreover, advanced communication devices must respond linearly therefore, linearity also studied. From brief investigation, exhibits negligible distortion in little or no compared SC-TFET. Thus, appropriate for ultra-low power high-frequency electronic devices.